Circuit for establishing accurate sample timing
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United States of America Patent
Stats
-
Mar 11, 1986
Grant Date -
N/A
app pub date -
Aug 30, 1984
filing date -
Sep 1, 1983
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
In order to establish accurate sample timing in a digital demodulator which forms part of an orthogonally multiplexed parallel data transmission system, two second-order PLLs are arranged after a demodulating section of the digital demodulator so as to receive baseband signals of corresponding pilot channels. The two second-order PLLs each includes an integrator. These integrators apply the outputs thereof to a subtracter which applies the subtraction result to a voltage-controlled oscillator in order to establish the accurate sample timing.
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