Importance

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Abstract

A refresh generator system for a dynamic memory in a data processing system, including a processor which is responsive to a hold request signal to relinquish control of the local bus and generate a hold acknowledge signal, comprises logic means to generate a hold request signal in response to an output from a refresh timer circuit. A logic circuit is responsive to a hold request, a corresponding hold acknowledge, and the timer signal to generate a refresh control signal. This signal generates a refresh signal for the memory control circuits, increments a counter circuit and initiates operation of a sequencer circuit. The sequencer then gates the output of the counter circuit to provide a memory row address and thereafter provides a memory read output to refresh the memory row defined by the address and lastly resets the circuit to terminate the hold request signal.

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First Claim