Low-inductance power/ground distribution in a package for a semiconductor chip
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United States of America Patent
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Mar 18, 1986
Issued Date -
N/A
app pub date -
Mar 2, 1984
filing date -
May 6, 1981
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A package for a semiconductor chip includes as an integral part thereof a frame-shaped multilayer ceramic capacitor. The chip is mounted within the capacitor structure. Conductive portions of the capacitor serve as the terminals and plates of the capacitor and as planar power and ground members for interconnecting an external power supply to the chip. By means of these planar members, power is distributed to the chip in a low-impedance, substantially transient-free manner without utilizing any of the multiple signal leds emanating from the package. Moreover, the signal leads are separated from the ground plane by a low-dielectric-constant material. As a result, the signal leads are minimally loaded and are characterized by a relatively constant impedance selected to optimize signal transfer to and from the chip.
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