Memory apparatus with random and sequential addressing
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United States of America Patent
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Apr 8, 1986
Grant Date -
N/A
app pub date -
Oct 25, 1982
filing date -
Nov 18, 1981
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A memory apparatus suitable for storing data for a high resolution bit mapped display includes large capacity (e.g. 64-k) semiconductor random access memory circuits in which to reduce the effective access time the circuits are operated and addressed in a repeating cycle including in succession reading from two or more addresses in sequence having the same row address component (i.e. in page mode), for example for the display, and writing into or reading from a randomly selected address.
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