Process for forming multi-layer interconnections

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United States of America Patent

PATENT NO 4582563
SERIAL NO

06675859

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Abstract

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First conductive members are buried in first holes formed in a first insulating film to connect the second interconnection layers, formed through first and second insulating films, to a semiconductor substrate. Second conductive members are buried in second holes formed to be positioned on the first holes of the second insulating film. Thus, the reliability of a semiconductor device of a multi-layer interconnection structure is improved, and the integration thereof is improved.

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Patent Owner(s)

Patent OwnerAddress
KABUSHIKI KAISHA TOSHIBA 72 HORIKAWA-CHO SAIWAI-KU KAWASAKI-SHI JAPAN A CORP OF JAPANNot Provided

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Hazuki, Yoshikazu Tokyo, JP 3 114
Moriya, Takahiko Yokosuka, JP 16 949

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