CMOS dynamic random-access memory with active cycle one half power supply potential bit line precharge
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United States of America Patent
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Apr 22, 1986
Grant Date -
N/A
app pub date -
Feb 22, 1984
filing date -
Feb 22, 1984
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A CMOS dynamic RAM is described which uses multiplexing to selectively couple two pairs of bit lines to a single sense amplifier. Both pairs of bit lines are decoupled from the sense amplifier after a word line selects a cell and before sensing occurs in the sense amplifier. Only one pair of bit lines is coupled to the input/output lines of the memory. No dummy cells are employed. The bit lines are charged to one-half the power supply potential. Restoration of potentials on each pair of bit lines occurs at different times, thereby reducing the peak currents to the RAM.
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