Bus oriented LIFO/FIFO memory
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
May 27, 1986
Grant Date -
N/A
app pub date -
Aug 31, 1983
filing date -
Aug 31, 1983
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
There is disclosed a modular memory cell structure including a data latch, an occupancy bit latch and control logic. Each memory cell has access to the occupancy bit status of adjacent cells and to the input, output, control, and status busses. The occupancy status provides positional address information enabling each cell to determine if data in its data latch is the first, intermediate, or last element of a data queue. When a group of memory cells and an initialization circuit are interconnected, a modular integrated circuit design results which can function as either a first in-first out (FIFO) or a last in-first out (LIFO) memory.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully