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Abstract

A microprocessor-controlled implantable programmable stimulator includes a pulse generator external to the microprocessor for producing stimulation output pulses to multiple electrodes. A single chip microprocessor accompanied by a ROM implements a stored program data processing system which sets various latches to establish the desired pulse parameters. Externally transmitted parameter data is decoded by the processing system, confirmed by two-way telemetry and loaded into control registers. The microprocessor obtains corresponding stored values from parameter tables in the ROM, and then sets the amplitude, rate and width latches. The pulse rate and width latches preset discrete rate and width down counters operated by respective slow and fast clocks. To conserve power, the fast clock is enabled only briefly each time the rate counter times out when it is time to issue an output pulse. When running, the fast clock replaces the slow clock input to the microprocessor. The timed-out signal from the rate counter generates an interrupt request to the microprocessor which calls a subroutine to reprogram electrode polarity before enabling each output pulse. This system allows several electrodes to be alternately connected as anodes and cathodes. An internal machine cycle counting routine disables the interrupt capability during the off portion of a scheduled on/off cycle and programs the rate to a fixed minimum. The continuous slow clock can be turned off by a reed switch whenever the rate counter is not in the timed-out condition. Reception of the first externally generated data pulse turns on the fast clock.

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First Claim