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Abstract

Method and apparatus for prefetching instructions for a pipelined central processor unit for a general purpose digital data processing system. A table is maintained for purposes of predicting the target addresses of transfer and indirect instructions based on past history of the execution of those instructions. The prefetch mechanism forms instruction addresses and fetches instructions in parallel with the execution of previously fetched instructions by a central execution pipeline unit of the central processor unit. As instructions are prefetched, the transfer and indirect prediction (TIP) table is checked to determine the past history of those instructions. If no transfers or indirects are found, the prefetch proceeds sequentially. If transfer or indirect instructions are found, then the prefetch uses information in the TIP table to begin fetching the target instruction(s). The purpose of the prediction of target addresses is so that in the usual case instructions following a transfer can be executed at a rate of one instruction per pipeline cycle regardless of the pipeline depth or the frequency of transfers. Instructions are fetched two words at a time in order that the instruction fetch unit can stay ahead of the central execution pipeline. An instruction stack is provided for purposes of buffering double words of instructions fetched by the instruction fetch unit while waiting for execution by the central execution pipeline unit. The TIP table is updated based upon the actual execution of instructions by the central execution pipeline unit, and the correctness of the TIP table predictions is checked during execution of every instruction.

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First Claim