Apparatus for performing quadratic convergence division in a large data processing system
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United States of America Patent
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Jun 10, 1986
Grant Date -
N/A
app pub date -
May 4, 1983
filing date -
May 4, 1983
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A binary division circuit for use in a large data processing system is disclosed which performs division with floating or fixed point numbers. It includes a multiplier unit which is modified to produce the higher precision calculation necessary to the division operation. This modification includes an augmented multiplier circuit which is combined with a quotient correction technique to provide a binary division circuit which produces identical quotients to those obtained by restoring or non-restoring divide techniques in less time than is required by other divide techniques.
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