Data processing technique for computer color graphic system
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United States of America Patent
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-
Jun 17, 1986
Grant Date -
N/A
app pub date -
Jun 13, 1983
filing date -
Jun 13, 1983
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A frame buffer, divided into three bit planes, is addressed by a single grahic display control chip, whose address signal is altered by an adder to address each bit plane at successive, prescribed time intervals during a single display cycle. A data word of N-bits from each of the first two bit planes is read and latched, then loaded simultaneously with a data word of N-bits from the third bit plane into corresponding shift registers. Thus, the number of memory chips in the frame buffer is minimized and three times the normal data output is achieved during each display cycle.
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