Electrically erasable programmable electronic circuits using programmable-threshold-voltage FET pairs
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United States of America Patent
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Jun 24, 1986
Issued Date -
N/A
app pub date -
Jul 5, 1984
filing date -
Sep 30, 1982
priority date (Note) -
Expired
status (Latency Note)
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Abstract
The series connection between operating voltage terminals of the channels of field effect transistors with electrically alterable threshold voltage, programmed one for conduction and the other for non-conduction in response to programming voltage on their gate-to-gate connection, forms a programmable latch. A pair of such latches, or such a latch and a complementary-pair logic inverter, form a programmable complemented latch. The programmable complemented latch can be used to selectively enable a complementary-pair transmission gate, or to selectively enable a complementary-pair logic inverter, or to alternatively enable a transmission gate and a logic inverter. This last operation can be carried out, for example, in a modified Annis exclusive-OR gate configuration, for selectively inverting or not inverting a logic input.
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