Clocked latching circuit
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United States of America Patent
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-
Jul 8, 1986
Grant Date -
N/A
app pub date -
May 13, 1983
filing date -
May 13, 1983
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A digital latching circuit includes a quantizer having an input pair of emitter-coupled transistors connected with output transimpedance circuits. The quantizer is responsive to the state of an input signal applied to the input pair for producing from the output transimpedance circuits a quantized output signal. A feedback pair of emitter-coupled transistors is interposed between the outputs of the transimpedance circuits and the inputs to the transimpedance circuits. Current pulses are applied alternatively to the common emitter circuits of the input pair and the feedback pair of transistors for alternatively enabling the quantizing of the state of the input signal and the latching of that quantized state.
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