Method for improving step coverage of dielectrics in VLSI circuits
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United States of America Patent
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Jul 22, 1986
Grant Date -
N/A
app pub date -
Oct 9, 1984
filing date -
Jun 15, 1984
priority date (Note) -
Expired
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Abstract
Particularly for use in multilevel metallization structures in which the underlying topography consists of fine and sharply contoured conductor lines produced by dry etching, conformal or near planar dielectric coatings are produced by depositing a dielectric layer to a thickness over the conductor of at least three times the conductor thickness. The dielectric is then anisotropically etched back to a thickness comparable with that of the underlying conductor. By this method a smooth dielectric top surface can be obtained without the requirement for multiple processing steps characterizing alternative planarizing techniques.
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