Importance

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Abstract

In a microcomputer system having a main memory accessed by both the CPU and the CRT controller, a page register system receives page bits defining both CPU and CRT pages from the CPU. The CPU page bits are combined with lower order address bits from the CPU for CPU access cycles, and the CRT page bits are combined with lower order address bits from CRT controller for CRT access cycles. Both the CPU and CRT controller can access any of the pages in the memory. For compatibility with higher level systems, the CPU may provide addresses in a range outside the range of addresses for the memory. When a decoder detects such addresses, it directs CPU address bits, corresponding in order to the CPU page bits, to address the memory instead of the CPU page bits.

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First Claim