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Abstract

The disclosure relates to error/fault detection in signal processing systems such as those employed in a time division multiplex conferencer. The digital message samples (of the conferees) and the accompanying parity bits are delivered to a signal processor e.g., a binary arithmetic adder (10). The adder sums the message samples and this sum is coupled to a first parity tree (11), which in response thereto generates a first parity bit. The carries generated by the summing operation and coupled to a second parity tree (12) along with the message parity bits and the second parity tree generates a second parity bit therefrom. The first and second parity bits are compared (13) and if they differ a fault exists. Corrective action is taken immediately--the faulty conference 'leg' is removed from the conference connection without affecting the remaining legs in the conference or any other conference.

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First Claim