Device for superimposition of the successive stages of the transfer of data among several data processing units
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Sep 9, 1986
Issued Date -
N/A
app pub date -
Mar 20, 1984
filing date -
Jan 21, 1980
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A control logic circuit (C) is provided in each unit such as processors andemories in a multiple processor data processing system. Each control logic circuit (C) is equipped with a priority circuit (P12) which at one input receives the eligible local calls (RQ.sub.i L) of the unit itself and at the other input receives external calls (RQ.sub.k) transmitted by the other units. The control logic circuit (C) enables control by its unit of a transmission but only when its priority circuit (P12) recognizes that unit as having the highest priority among the other units. The logic circuit (C) together with a T circuit (13) selects local calls as a function of the state of occupation of the data lines of the transmission bus.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully