Method and structure for use in designing and building electronic systems in integrated circuits

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United States of America Patent

PATENT NO 4613940
SERIAL NO

06440283

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Abstract

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A method of designing an integrated circuit layout based on primitive elements such as transistors, resistors, and conductors and cell structures formed from the primitive functional element. The primitive elements are defined by surface dimensions, semiconductor construction, and surface layers and can be placed to accommodate special cell structures and functions. Design time can be minimized by using preexisting cell structures stored in suitable computer means, or layout surface and production costs can be minimized by designing new cell structures using a simple technique. Process independence can be achieved by having a complete design based on a small number of primitive elements which can be readily modified.

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Patent Owner(s)

Patent OwnerAddress
SILICON VALLEY BANK3003 TASMAN DRIVE SANTA CLARA CA 95054

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Barton, Ronald E Saratoga, CA 1 181
Jones, Ioan G Los Gatos, CA 1 181
Lucas, David W Saratoga, CA 4 273
Shenton, Graham Monte Sereno, CA 1 181

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