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Abstract

An improved means and method is described for providing a conductive pillar in a via between multiple layers of conductors on planar electronic structures such as integrated circuits. A lower first conductor layer is formed on the device substrate and covered with an electrically conducting etch-stop layer and a second conductor layer. The second conductor layer is masked to define the conductive via and etched selectively and anisotropically until the etch-stop layer is reached. The exposed portions of the etch-stop layer are then removed. The remaining portions of the etch-stop layer and second conductor layer together form the conductive pillar. The lower first metal layer is patterned and then covered with a planarizing layer, such as a polyimide, having a thickness at least equal to the height of the pillar. The planarizing layer is uniformly etched to expose the top of the pillar and then an upper metal layer deposited over the remaining polyimide and in contact with the top of the pillar. The remaining polyimide acts as the interlayer dielectric.

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First Claim