System memory for a reduction processor evaluating programs stored as binary directed graphs employing variable-free applicative language codes
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United States of America Patent
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Oct 7, 1986
Grant Date -
N/A
app pub date -
Jan 11, 1985
filing date -
Jan 11, 1985
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A system memory for a reduction processor which evaluates programs stored as binary graphs employing variable-free applicative language codes. These graphs are made up of nodes, each of which exists in memory and contains as its most significant bit a mark bit which when set indicates that the node is being used in a graph and when reset indicates that the node or storage location is available for future use by the processor. In order to accommodate the scanning of a number of storage locations in parallel, the system memory is divided into a node memory and the mark bit memory so that the mark bits for a number of sequential storage locations can be examined in parallel to determine which node locations are free for use by the graph manager.
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