Adjustable time delay circuit
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Oct 21, 1986
Grant Date -
N/A
app pub date -
Dec 9, 1983
filing date -
Dec 9, 1983
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
An adjustable time delay circuit 10, 50 includes a time delay line 12 including a plurality of series connected time delay units 18a-p. During adjustment, sampled signals along the delay line 12 are compared with a reference signal by NOR-gates 22e-m. Upon a comparison being attained, the output of the corresponding NOR-gate 22e-m sets a selected flip-flop 30e-m which in turn routes the signal at a selected delay line tap 38e-m through a NOR-gate 34e-m to an output OR-gate 40. The tap 38e-m selected, compensates for component propagation characteristics thus maintaining a predetermined time delay through the time delay circuit 10.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully