Dynamic memory with improved address counter for serial modes
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United States of America Patent
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Oct 21, 1986
Grant Date -
N/A
app pub date -
Jul 26, 1984
filing date -
Jul 26, 1984
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A semiconductor dynamic read/write memory device has serial data input/output modes, such as the so-called nibble, byte or extended nibble modes. This device employs improved address counter circuitry to access data from a selected row. An initial column address is latched when a serial mode is initiated, and the counter steps through the programmed number of bits, starting at the initial address. The number of bits used in the serial mode may be selected by metal-mask programming. To avoid a speed penalty, look-ahead circuitry initiates the set up for serial mode before the controls for this mode are detected.
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