Enhanced reliability interrupt control apparatus
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United States of America Patent
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Dec 16, 1986
Grant Date -
N/A
app pub date -
Jan 9, 1984
filing date -
Jan 31, 1983
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
Interrupt control apparatus in a data processing system for acknowledging on a priority basis one among several possible asynchronous interruptions (INT1, INTN), such apparatus comprising a priority network (5), a latching (7) and a validation circuit (11,12). The priority network directly receives on its input terminals the asynchronous interrupt signals and provides on its output terminals a binary code corresponding to the highest priority interrupt present on its input terminals. The interrupt code is latched in the register and is present on its output terminals. The code latched in the register is used by a validation circuit as a selection code of the related input interrupt signal. If such a signal is present, the code is validated, i.e., it is transferred to the central unit of the system. If the selected interrupt signal is not present, the code is not validated.
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