Time multiplexed processor bus
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United States of America Patent
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-
Dec 16, 1986
Grant Date -
N/A
app pub date -
Sep 23, 1982
filing date -
Apr 27, 1981
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A multi-master processor bus and a method of processing data which permits multiple microprocessors to communicate freely and inexpensively among themselves and various system resources. The bus uses a multiphase clock and latches to provide time slice signals to sequentially activate each processor, one at a time in a repetitive sequence. The bus includes cables and terminals for each of the cables with means for interconnecting each of the modules in series daisy chain fashion to selected cables.
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