Memory interface with automatic delay state
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United States of America Patent
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-
Dec 23, 1986
Issued Date -
N/A
app pub date -
Apr 1, 1985
filing date -
Mar 8, 1984
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A digital processor system that includes a processor interface to an external memory. The interface to the external memory includes an information transfer bus to transfer information between the processor and the external memory and control circuitry to regulate the information on the information bus. This control circuitry includes the capability to delay the reading of information on the memory in order to allow for memory accesses to a slow memory. This delay capability is a selectable feature that is selected upon initialization of the processor.
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