Importance

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Abstract

A system and method are disclosed for automatically refreshing a dynamic random access memory (DRAM) under a plurality of different operational conditions of an associated processor. When the processor is normally executing instructions it generates active signals which enable a generator circuit to generate timing signals. A hidden refresh circuit uses status signals and a first part of these timing signals to generate a refresh pulse during an opcode fetch cycle of each instruction being executed by the processor. A control circuit uses each refresh pulse and a second part of the timing signals to generate a row refresh signal to refresh a row in the DRAM indicated by a row address from a counter and a row address clock to increment the counter to the next row to be refreshed by the following row refresh signal. When a keep alive circuit senses that the processor has not run for a preselected period of time due to the incircuit use of a piece of test equipment, it generates pulses to enable the hidden refresh circuit to cause the control circuit to periodically refresh the DRAM until after the processor starts running again. When a halt/power-down circuit senses that the processor is executing a HALT instruction, it forces the processor to branch off into a subroutine to execute a preselected number of instructions to refresh an associated number of rows before allowing the processor to return to its HALT instruction. This operation periodically repeats until the processor has completed its HALT instruction.

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First Claim