Importance

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Abstract

A digital signal processor (10) has a crossbar network (110) interconnecting a control and timing circuit (100), a multiplier (112), a serial access data memory (128), temporary storage registers (122, 124, 126), an accumulator (120) and input and output inferfaces (130, 132). Instructions in an external memory (12) are decoded by the control and timing circuit to cause the crossbar network to interconnect the other circuit elements in various patterns to feed selected signals from the input interface and stores to the multiplier, and the multiplier results to the stores and output interface. The sequence of interconnection patterns can be chosen to provide a selected signal processing function such as filtering. A multiplicand register (116) and a substitution circuit (118) enable the data to be modified in transit to implement other more complex signal processing functions.

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