Importance

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Abstract

A large capacity (8 memory banks of 524K error-corrected 36 bit words stored) high performance (latency as low as 240 nanoseconds, 12.8 gigabits/second aggregate data transfer capability with up to 11.4 gigabits/second utilized) pipelined (8 deep request pipeline) random access memory store simultaneously (to the limit of bank addressing conflicts) services intermixed requests from an internal exerciser plus ported requestors (up to 10) of plural types (3 types), which requestors are not of the same interface cycle time (30 nsec vs. 60 nsec). Furthermore, to such nonuniform interface cycle times, the bit-width of the data transfer interfaces (ports) to the requestors of plural types is also not uniform, but is actually wider (4 interface words of 36 bits each=144 bits) to faster (30 nanosecond) requestors than is that data transfer bit-width (2 interface words=72 bits) to slower (60 nsec) requestors. Three differing individual requestor bandwidths=data-transfer-bit width/data-transfer-period (144 bits/30 nanosecond, 72 bits/120 nanosecond or 248 bits/240 nanosecond) are intermixedly and simultaneously (to the limit of addressing possibility) supported on 8 memory banks each of which does output 144 bits per 90 nanoseconds.

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First Claim