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Abstract

A field effect transistor (FET) structure suitable for MOS and CMOS IC fabrication processes includes spaced apart alternating source and drain regions distributed in a rectangular checkerboard pattern of horizontal and vertical rows. A first grid of intersecting horizontal and vertical conductive gate lines overlaps adjacent source and drain regions of the array and is dielectrically isolated from the source and drain regions by an insulating layer. The horizontal and vertical gate lines provide a single gate element distributed across the array which reduces FET channel length and channel resistance. A second grid comprising a set of parallel diagonal alternating source lead lines and drain lead lines is dielectrically isolated from the first grid. The source lead lines are electrically coupled to source regions and drain lead lines to drain regions. The second grid includes a first metal layer of diagonal source and drain lead lines and a second metal layer overlying at least a portion of the first metal layer. The first and second metal layers are selectively coupled to reduce current density and resistance in the diagonal lead lines without increasing the width of the lead lines. Back contact areas or regions are distributed around the perimeter of the checkerboard pattern forming a back contact guard ring or band.

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First Claim