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Abstract

An interface facilitating data transmission between a control processor, connected to an asynchronous two-way bus, and a plurality of terminals, connected to a common synchronous two-way bus, comprises a microprocessor responsive to periodically recurring access requests from the several terminals. The access requests are short pulses with a recurrence period greatly exceeding their duration, this period being nominally equal for all terminals and sufficient to accommodate one data transfer to or from each terminal with time remaining for execution of part of a main program performed by the control processor. Coinciding access requests from different terminals are handled according to a predetermined order of priority. The exchange of data takes place by way of a data memory and a buffer memory linked by an internal two-way bus. Data transfer between the control processor and a terminal takes place in three stages, i.e. between the processor and the buffer memory, between the buffer memory and the data memory, and between the data memory and the terminal. Except during the second stage, the processor has always access to the buffer memory.

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First Claim