Importance

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Abstract

A pipelined data processor is described, which obeys a sequence of instructions each with a read phase in which an operand is read from a memory, an execute phase in which an operation is performed by an execution unit, and a write phase in which a result is written into the memory. The phases of successive instructions are overlapped, and each instruction is stepped on to its next phase at the end of each clock beat. Each clock beat is divided into a write sub-beat followed by two read sub-beats. The write address for each instruction is stored in a write address register and is compared with each read or write address applied to the memory. When these addresses match, the output of the execution unit is either written into the memory (if the match occurs during a write sub-beat) or fed back to the execution unit as an operand (if the match occurs during a read sub-beat). In the latter case, the operand is made available to the next instruction without having to pass through the memory, and this overcomes the problem of a read/write clash, where one instruction requires to read an operand which has not yet been written by the preceding instruction.

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First Claim