Level-shifting circuit
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Feb 10, 1987
Grant Date -
N/A
app pub date -
Jun 11, 1985
filing date -
Jun 12, 1984
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A level shifting circuit in which the collectors of a first transistor and a second transistor (T.sub.1, T.sub.2), which are coupled together as a differential pair, are each connected to a load resistor (R.sub.o) and to the base of a third transistor and a fourth transistor (T.sub.3, T.sub.4), respectively, which are connected as emitter followers. In order to obtain a low dissipation for a specific gain and bandwidth, the collector of the third transistor (T.sub.3) is coupled to a tapping (7) on the load resistor (R.sub.o) of the second transistor (T.sub.2) and the collector of the fourth transistor (T.sub.4) is coupled to a tapping (6) on the load resistor (R.sub.o) of the first transistor (T.sub.1).
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully