Special interconnect for configurable logic array
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United States of America Patent
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Feb 10, 1987
Grant Date -
N/A
app pub date -
Sep 26, 1984
filing date -
Sep 26, 1984
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A special interconnect circuit which connects adjacent configurable logic elements (CLEs) in a configurable logic array (CLA) without using the general interconnect structure of the CLA. In one embodiment, an array of CLEs is arranged in rows and columns and a special vertical lead circuit is provided which connects an output lead of a given CLE in a given column to a selected input lead of the CLE above it and below in the same column. Special horizontal lead circuits are provided which connect a given output lead of a given CLE to a selected adjacent input lead of the CLE in the same row.
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