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Abstract

A semiconductor memory device used, for example, for a video RAM device which stores picture data and which is used in a video display device, etc. The semiconductor memory device includes an internal address generating circuit which sequentially generates row addresses, an address switching circuit which switches between the row address output from the internal address generating circuit and an external address, and a plurality of internal shift registers each of which stores a plurality of bit data which is read out in parallel from a memory cell array in accordance with the internal row address and/or a plurality bit data which is written-in parallel to the memory cell array in accordance with the internal row address. A serial input/output control circuit for controlling the shift registers is also provided. The input/output control circuit controls each of the shift registers so that each of the shift registers effects a shift operation to serially and continuously input or output data. When a memory cell array is not accessed by an external circuit during a time period in which a plurality of bit data is serially input or output to or from one of the plurality of shift registers, the input/output control circuit effects a parallel write-in or readout operation, in accordance with the next row address, to or from the memory cell array.

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First Claim