Computer memory system with integrated parallel shift circuits
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United States of America Patent
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Feb 17, 1987
Grant Date -
N/A
app pub date -
Dec 30, 1983
filing date -
Dec 30, 1983
priority date (Note) -
Expired
status (Latency Note)
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Abstract
The system includes a plurality of memory units each for storing a plurality of independently addressable binary bits. The units operate together in response to each common bit address to supply a bit from each unit to form an array of bits for a discrete section of a larger array. The units are interconnected through common interconnection buses and selectively actuable input and output gate connections to those buses to provide for selective shifting of bits between units to change the bit array.
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