Importance

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Abstract

This invention provides a high-speed switching processor which may be employed as a component of a link switch or a hub switch in a burst-switching communications system. When so employed, transmission speeds for integrated voice and data services over communications links between switches may be equivalent to the T1 rate or higher. A burst is a plurality of bytes which represents, for example, a block of data or a spurt of voice energy sensed by silence/voice detectors located at voice ports. In a preferred embodiment, the architecture of the switching processor includes a data/address bus, control including a stored program in a 64-bit wide PROM, a finite-state machine having character and channel states for generating a jump address in the stored program based on the status of an incoming burst, interfaces with other components of the switch such as the queue sequencer, a companion processor, and a dual-port RAM for generating a buffer address as a function of channel number for the dynamic buffer in character memory in which the incoming burst is being stored. In this architecture, most components of the switching processor operate substantially in parallel with and independently of the control which is a contributing factor to the overall speed advantage realized by the switching processor. With software or firmware variations, the switching processor may be employed as several different components of a link or hub switch.

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First Claim