
US Patent No: 4,646,299
Number of patents in Portfolio can not be more than 2000
Method and apparatus for applying and monitoring programmed test signals during automated testing of electronic circuits
Stats
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Feb 24, 1987
Issued date -
May 17, 1984
filing date -
06/611,445
serial no -
Expired
status

Importance
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US Family Size
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Patent Longevity
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Forward Citations
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Abstract
A plurality of test signal applying and monitoring circuits are coupled to pins of an electronic device being tested to force test stimuli signals onto input pins of the device under test. The response signals are monitored while the device is being tested. Each test signal applying and monitoring circuit includes a node to be coupled to a pin of the device under test, a digitally programmed source for supplying a test signal connectable to the node by a first switch, and a comparison circuit connected to the node by a second switch for indicating the relative amplitude of the response signal with respect to a programmed reference level. The digitally programmed source is included for providing gated voltage-current crossover forcing functions during functional testing to minimize the disturbance when the device being tested is connected and to protect out of tolerance devices. Programmable voltage and current values define a pass window to assure a non-ambiguous go/no-go result during testing. Other features are also disclosed.
First Claim
Related Publications
- 15 United States
- 10 France
- 8 Japan
- 7 China
- 5 Korea
- 2 Other
Patent Owner(s)
| Patent Owner | Address | Total Patents |
|---|---|---|
| FAIRCHILD CAMERA & INSTRUMENT CORP. | MOUNTAIN VIEW, CA | 251 |
| NATIONAL SEMICONDUCTOR CORPORATION | SANTA CLARA, CA | 4706 |
| SCHLUMBERGER SYSTEMS AND SERVICES, INC. | SUNNYVALE, CA | 68 |
International Classification(s)
- [Classification Symbol]
- [Patents Count]
Inventor(s)
| Inventor Name | Address | # of filed Patents | Total Citations |
|---|---|---|---|
| Murdock, James R | Tolland, CT | 7 | 158 |
| Schinabeck, John | Pleasanton, CA | 3 | 226 |
Cited Art
| Patent Info | (Count) | # Cites | Year |
|---|---|---|---|
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| 4,271,515 Universal analog and digital tester | 16 | 1979 | |
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| 4,517,512 Integrated circuit test apparatus test head | 103 | 1982 | |
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| 4,523,312 IC tester | 39 | 1982 | |
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| 4,439,858 Digital in-circuit tester | 59 | 1981 | |
Patent Citation Ranking
Forward Cites
| Patent Info | (Count) | # Cites | Year |
|---|---|---|---|
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| 5,913,020 Method for using fuse identification codes for masking bad bits on single in-line memory modules | 16 | 1997 | |
| 7,065,682 Method for monitoring tests run on a personal computer | 0 | 1997 | |
| 6,441,627 Socket test device for detecting characteristics of socket signals | 5 | 1998 | |
| 6,496,876 System and method for storing a tag to identify a functional storage location in a memory device | 3 | 1998 | |
| 6,202,030 Calibrating test equipment | 3 | 1999 | |
| 6,578,157 Method and apparatus for recovery of useful areas of partially defective direct rambus rimm components | 4 | 2000 | |
| 7,269,765 Method and apparatus for storing failing part locations in a module | 41 | 2000 | |
| 6,810,492 Apparatus and system for recovery of useful areas of partially defective direct rambus RIMM components | 3 | 2003 | |
| 7,328,381 Testing system and method for memory modules having a memory hub architecture | 8 | 2005 | |
| 7,319,340 Integrated circuit load board and method having on-board test circuit | 20 | 2005 | |
| 7,765,424 System and method for injecting phase jitter into integrated circuit test signals | 0 | 2005 | |
| 7,355,387 System and method for testing integrated circuit timing margins | 3 | 2005 | |
| 7,284,169 System and method for testing write strobe timing margins in memory devices | 4 | 2005 | |
| 7,890,819 Method and apparatus for storing failing part locations in a module | 0 | 2007 | |
| 7,521,948 Integrated circuit load board and method having on-board test circuit | 0 | 2007 | |
| 7,619,404 System and method for testing integrated circuit timing margins | 1 | 2007 | |
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| 5,265,101 Function array sequencing for VLSI test system | 2 | 1989 | |
| 4,928,062 Loading and accurate measurement of integrated dynamic parameters at point of contact in automatic device handlers | 19 | 1989 | |
| 6,728,915 IC with shared scan cells selectively connected in scan path | 7 | 2001 | |
| 6,769,080 Scan circuit low power adapter with counter | 7 | 2001 | |
| 7,058,862 Selecting different 1149.1 TAP domains from update-IR state | 9 | 2001 | |
| 6,763,485 Position independent testing of circuits | 12 | 2002 | |
| 6,975,980 Hierarchical linking module connection to access ports of embedded cores | 2 | 2002 | |
| 6,996,761 IC with protocol selection memory coupled to serial scan path | 2 | 2003 | |
| 6,990,620 Scanning a protocol signal into an IC for performing a circuit operation | 1 | 2003 | |
| 7,058,871 Circuit with expected data memory coupled to serial input lead | 3 | 2003 | |
| 6,898,544 Instruction register and access port gated clock for scan cells | 1 | 2004 | |
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| 5,596,587 Method and apparatus for preparing in-circuit test vectors | 28 | 1993 | |
| 5,682,392 Method and apparatus for the automatic generation of boundary scan description language files | 29 | 1996 | |
| 6,133,725 Compensating for the effects of round-trip delay in automatic test equipment | 27 | 1998 | |
| 6,194,910 Relayless voltage measurement in automatic test equipment | 6 | 1998 | |
| 6,374,379 Low-cost configuration for monitoring and controlling parametric measurement units in automatic test equipment | 7 | 1999 | |
| 7,216,273 Method for testing non-deterministic device data | 4 | 2003 | |
| 7,403,030 Using parametric measurement units as a source of power for a device under test | 2 | 2004 | |
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| 6,332,183 Method for recovery of useful areas of partially defective synchronous memory components | 2 | 1998 | |
| 6,314,527 Recovery of useful areas of partially defective synchronous memory components | 3 | 1998 | |
| 6,381,707 System for decoding addresses for a defective memory array | 12 | 1998 | |
| 6,381,708 Method for decoding addresses for a defective memory array | 4 | 1998 | |
| 6,621,748 Recovery of useful areas of partially defective synchronous memory components | 0 | 2001 | |
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| 5,293,374 Measurement system control using real-time clocks and data buffers | 13 | 1992 | |
| 5,578,932 Method and apparatus for providing and calibrating a multiport network analyzer | 141 | 1995 | |
| 5,552,714 Electronic calibration method and apparatus | 25 | 1995 | |
| 7,739,070 Standardized interfaces for proprietary instruments | 0 | 2007 | |
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| 5,353,243 Hardware modeling system and method of use | 31 | 1992 | |
| 5,625,580 Hardware modeling system and method of use | 41 | 1994 | |
| 5,673,295 Method and apparatus for generating and synchronizing a plurality of digital signals | 16 | 1995 | |
| 6,148,275 System for and method of connecting a hardware modeling element to a hardware modeling system | 1 | 1997 | |
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| 5,225,772 Automatic test equipment system using pin slice architecture | 28 | 1990 | |
| 5,212,443 Event sequencer for automatic test equipment | 40 | 1990 | |
| 8,295,182 Routed event test system and method | 0 | 2008 | |
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| 6,476,627 Method and apparatus for temperature control of a device during testing | 49 | 1996 | |
| 6,650,132 Method and apparatus for temperature control of a device during testing | 7 | 2002 | |
| 6,788,084 Temperature control of electronic devices using power following feedback | 5 | 2002 | |
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| 5,101,153 Pin electronics test circuit for IC device testing | 70 | 1991 | |
| 5,414,352 Parametric test circuit with plural range resistors | 11 | 1993 | |
| 5,377,202 Method and apparatus for limiting pin driver offset voltages | 15 | 1993 | |
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| 6,812,691 Compensation for test signal degradation due to DUT fault | 68 | 2002 | |
| 7,245,120 Predictive, adaptive power supply for an integrated circuit under test | 3 | 2005 | |
| 7,714,603 Predictive, adaptive power supply for an integrated circuit under test | 2 | 2007 | |
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| 5,579,236 Voltage/current measuring unit and method | 7 | 1996 | |
| 6,639,397 Automatic test equipment for testing a device under test | 19 | 2001 | |
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| 7,839,158 Method of detecting abnormality in burn-in apparatus | 0 | 2005 | |
| 7,802,160 Test apparatus and calibration method | 0 | 2007 | |
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| 5,467,024 Integrated circuit test with programmable source for both AC and DC modes of operation | 84 | 1993 | |
| 5,617,035 Method for testing integrated devices | 108 | 1995 | |
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| 4,983,907 Driven guard probe card | 72 | 1989 | |
| 6,732,053 Method and apparatus for controlling a test cell | 3 | 1998 | |
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| 5,761,214 Method for testing integrated circuit devices | 3 | 1992 | |
| 6,054,863 System for testing circuit board integrity | 3 | 1996 | |
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| 6,563,298 Separating device response signals from composite signals | 9 | 2000 | |
| 6,703,825 Separating device response signals from composite signals | 6 | 2003 | |
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| 6,727,834 Method and device for use in DC parametric tests | 3 | 2003 | |
| 6,917,320 Method and device for use in DC parametric tests | 0 | 2004 | |
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| 6,876,206 Automatic jack tester | 0 | 2002 | |
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| 5,493,519 High voltage driver circuit with fast current limiting for testing of integrated circuits | 7 | 1993 | |
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| 5,210,832 Multiple domain emulation system with separate domain facilities which tests for emulated instruction exceptions before completion of operand fetch cycle | 24 | 1991 | |
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| 5,010,297 Automatic test equipment with active load having high-speed inhibit mode switching | 9 | 1989 | |
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| 5,392,293 Built-in current sensor for I.sub.DDQ testing | 58 | 1993 | |
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| 5,740,352 Liquid-crystal display test system and method | 12 | 1995 | |
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| 4,771,428 Circuit testing system | 24 | 1986 | |
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| 5,025,344 Built-in current testing of integrated circuits | 56 | 1990 | |
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| 6,194,909 Constructive module of an electronic telecommunications equipment, with an interface towards a testing and diagnosing system | 3 | 1998 | |
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| 6,396,256 Power supply slew time testing of electronic circuits | 1 | 1998 | |
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| 4,827,437 Auto calibration circuit for VLSI tester | 28 | 1986 | |
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| 5,842,155 Method and apparatus for adjusting pin driver charging and discharging current | 12 | 1993 | |
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| 7,969,171 Test circuit and system | 0 | 2010 | |
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| 5,390,194 ATG test station | 13 | 1993 | |
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| 7,681,081 Test device and method for testing stability of computer | 0 | 2006 | |
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| 5,047,971 Circuit simulation | 32 | 1989 | |
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| 7,724,017 Multi-channel pulse tester | 0 | 2006 | |
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| 6,101,458 Automatic ranging apparatus and method for precise integrated circuit current measurements | 4 | 1997 | |
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| 6,885,213 Circuit and method for accurately applying a voltage to a node of an integrated circuit | 16 | 2003 | |
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| 5,648,918 Calibration of a plurality of excitation sources for an instrumentation system | 12 | 1995 | |
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| 5,286,656 Individualized prepackage AC performance testing of IC dies on a wafer using DC parametric test patterns | 76 | 1992 | |
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| 4,849,847 Power supply switch for wafer scale applications | 20 | 1987 | |
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| 4,875,006 Ultra-high-speed digital test system using electro-optic signal sampling | 46 | 1988 | |
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| 6,842,712 Method for testing an electronic component; computer program product, computer readable medium, and computer embodying the method; and method for downloading the program embodying the method | 0 | 2003 | |
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| 7,129,719 Apparatus for detecting defect in circuit pattern and defect detecting system having the same | 0 | 2004 | |
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| 6,031,386 Apparatus and method for defect testing of integrated circuits | 11 | 1997 | |
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| 6,489,793 Temperature control of electronic devices using power following feedback | 56 | 1999 | |
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| 7,055,135 Method for debugging an integrated circuit | 1 | 2002 | |
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| 5,973,504 Programmable high-density electronic device testing | 97 | 1997 | |
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| 7,685,479 Telecommunications network testing | 0 | 2006 | |
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| 7,231,573 Delay management system | 1 | 2002 | |
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| 8,306,770 Method, system and test platform for testing output of electrical device | 0 | 2010 | |
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| 4,707,849 High speed automatic test apparatus especially for electronic directory terminals | 6 | 1986 | |
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Maintenance Fees
| Fee | Large entity fee | small entity fee | micro entity fee | due date |
|---|
| Fee | Large entity fee | small entity fee | micro entity fee |
|---|---|---|---|
| Surcharge after expiration - Late payment is unavoidable | $700.00 | $350.00 | $175.00 |
| Surcharge after expiration - Late payment is unintentional | $1,640.00 | $820.00 | $410.00 |