Process of making interconnection structure for semiconductor device
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Mar 10, 1987
Grant Date -
N/A
app pub date -
Jun 30, 1983
filing date -
Jun 30, 1983
priority date (Note) -
Expired
status (Latency Note)
![]() |
A preliminary load of PAIR data current through [] has been loaded. Any more recent PAIR data will be loaded within twenty-four hours. |
PAIR data current through []
A preliminary load of cached data will be loaded soon.
Any more recent PAIR data will be loaded within twenty-four hours.
![]() |
Next PAIR Update Scheduled on [ ] |

Importance
|
US Family Size
|
Non-US Coverage
|
Patent Longevity
|
Forward Citations
|
Abstract
A first level interconnection structure is fabricated by forming conductor patterns on the top surface of a thin flexible polymer film temporarily supported on a rigid thin ceramic or metal support member having windows therein. Via openings in the bottom surface of the polymer film are made to selected conductors, and the openings are filled with bonding metallurgy. The lower surface of the film is coated with a partially cured polyimide adhesive. The adhesive is removed in the via areas to expose the bonding metallurgy. This first layer structure is tested and then transferred to the ceramic substrate of a VSLI circuit interconnection module on which corresponding metal pads are formed for pad-to-pad contact. When pressure and heat are applied, there occurs simultaneous bonding of the metal pads on the substrate and of the film directly to the substrate. A second level interconnection structure is formed in the same manner and bonded to the top surface of the first level structure. Additional level structures may be similarily superimposed to form a multilayer interconnection structure. During bonding, the lamination of the layers occurs in such a way that a single solid film is formed with the conductors embedded therein. One or more integrated circuit chips may then be bonded by their contact pads to the conductors on the upper most level interconnection structure.
First Claim
Family
- 15 United States
- 10 France
- 8 Japan
- 7 China
- 5 Korea
- 2 Other
Patent Owner(s)
| Patent Owner | Address | |
|---|---|---|
| INTERNATIONAL BUSINESS MACHINES CORPORATION | NEW ORCHARD ROAD ARMONK NY 10504 |
International Classification(s)
Inventor(s)
| Inventor Name | Address | # of filed Patents | Total Citations |
|---|---|---|---|
| Bhattacharyya, Arup | Essex Junction, VT | 228 | 9935 |
| Wen, Ho Chung | Chappaqua, NY | 1 | 54 |
Cited Art Landscape
- No Cited Art to Display

Patent Citation Ranking
Forward Cite Landscape
- No Forward Cites to Display

Maintenance Fees
| Fee | Large entity fee | small entity fee | micro entity fee | due date |
|---|
| Fee | Large entity fee | small entity fee | micro entity fee |
|---|---|---|---|
| Surcharge after expiration - Late payment is unavoidable | $700.00 | $350.00 | $175.00 |
| Surcharge after expiration - Late payment is unintentional | $1,640.00 | $820.00 | $410.00 |
Full Text
Legal Events
Matter Detail
Update Public Data
Dismiss
Edit
Save
Renewals Detail
Edit
Save
Note
The template below is formatted to ensure compatibility with our system.
Provide tags with | separated like (tags1|tags2).
Maximum length is 128 characters for Customer Application No
Mandatory Fields * - 'MatterType','AppType','Country','Title','SerialNo'.
Acceptable Date Format - 'MM/DD/YYYY'.
Acceptable Filing/App Types -
- Continuation/Divisional
- Original
- Paris Convention
- PCT National
- With Priority
- EP Validation
- Provisional Conversion
- Reissue
- Provisional
- Foreign Extension
Acceptable Status -
- Pending
- Abandoned
- Unfiled
- Expired
- Granted
Acceptable Matter Types -
- Patent
- Utility Model
- Supplemental Protection Certificate
- Design
- Inventor Certificate
- Plant
- Statutory Invention Reg
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Success
E-mail has been sent successfully.
Failure
Some error occured while sending email. Please check e-mail and try again!
PAIR load has been initiated
A preliminary load of cached data will be loaded soon. Current PAIR data will be loaded within twenty four hours.
File History PDF
Thank you for your purchase! The File Wrapper for Patent Number 4648179 will be available within the next 24 hours.
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully
Important Notes on Latency of Status data
Please note there is up to 60 days of latency in this Status indicator for certain status conditions. You can obtain up-to-date Status indicator readings by ordering PAIR for the file.
An application with the status "Published" (which means it is pending) may be recently abandoned, but not yet updated to reflect its abandoned status. However, an application filed less than one year ago is unlikely to be abandoned.
A patent with the status "Granted" may be recently expired, but not yet updated to reflect its expired status. However, it is highly unlikely a patent less than 3.5 years old would be expired.
An application with the status "Abandoned" is almost always current, but there is a small chance it was recently revived and the status not yet updated.
Important Note on Priority Date data
This priority date is an estimated earliest priority date and is purely an estimation. This date should not be taken as legal conclusion. No representations are made as to the accuracy of the date listed. Please consult a legal professional before relying on this date.
We are sorry but your current selection exceeds the maximum number of portfolios (0) for this membership level. Upgrade to our Level for up to -1 portfolios!.
