Importance

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Abstract

A clocked comparator comprising a comparison stage, for comparing an analog input voltage V.sub.IN with an analog reference voltage V.sub.REF and for supplying. An intermediate signal V.sub.M and its complement V.sub.M, an amplifier stage amplifies the logic states of the intermediate signal. A first and a second latching stage are coupled to the comparison stage and the amplifier stage respectively, for generating and storing the logic states determined by the signals from the comparison stage and the amplifier stage. Each latching stage comprises a differential transistor pair having a common terminal connected to ground. A further differential transistor pair is arranged in parallel with the last-mentioned transistor pair and is controlled by a clock signal C for the first latching stage and by its complement C for the second latching stage. The comparison stage and the amplifier stage are also controlled by the clock signal C and the latching stages are each coupled to the comparison stage and the amplifier stage respectively by means of load resistors. Useful in a digital/analog converter equipped with enhancement-type gallium-arsenide field-effect transistors.

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