Dynamic row buffer circuit for DRAM
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United States of America Patent
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Mar 10, 1987
Grant Date -
N/A
app pub date -
Jun 1, 1984
filing date -
Jun 1, 1984
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Expired
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Abstract
A dynamic row buffer circuit is disclosed for a dynamic random access memory (DRAM) chip which enables the DRAM chip to be used for special function applications. The dynamic row buffer comprises a row buffer master register and a row buffer slave register. The row buffer master register comprises a plurality of master circuits (M1) and a plurality of slave circuits (S1). Likewise, the row buffer slave register comprises a plurality of master circuits (M2) and a plurality of slave circuits (S2). The row buffer master register is parallel load and parallel read-out with the outputs of the master register slave circuits being connected to the master circuits of the slave register. The row buffer slave register is a parallel load, serial read-out register with the output being shifted out of a secondary output port. The entire row buffer can be isolated from the memory array, and when so isolated, the memory array can be accessed through the primary input/output port in the same way as in an ordinary DRAM chip. This arrangement permits the conversion of a DRAM chip to a dual port display, of which a specific example is disclosed, or some other special function RAM thereby adding a large value to the DRAM chip with little additional cost.
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- 15 United States
- 10 France
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Patent Owner(s)
- INTERNATIONAL BUSINESS MACHINES CORPORATION
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Inventor(s)
Inventor Name | Address | # of filed Patents | Total Citations |
---|---|---|---|
Chung, Paul W | San Jose, CA | 11 | 205 |
Ling, Daniel T | Croton-on-Hudson, NY | 10 | 548 |
Matick, Richard E | Peekskill, NY | 21 | 1003 |
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Fee | Large entity fee | small entity fee | micro entity fee |
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Surcharge after expiration - Late payment is unavoidable | $700.00 | $350.00 | $175.00 |
Surcharge after expiration - Late payment is unintentional | $1,640.00 | $820.00 | $410.00 |
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