Importance

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Abstract

Synchronization facilities are disclosed for maintaining error free timing of a digital system when control of the system timing is switched between a plurality of clock sources. The signal of each source is applied to an associated counter divider whose output is applied to switch facilities which extend the output of only one divider at a time as a reference clock source to the digital system. The dividers for the other sources are forcibly reset each time the divider of the reference source advances from its all 1s to its reset (all 0s) position. This maintains the output signals of all dividers in phase with each other to prevent disturbances to the digital system when its timing is switched between clock sources.

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First Claim