Asynchronous multiport parallel access memory system for use in a single board computer system
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United States of America Patent
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Mar 31, 1987
Grant Date -
N/A
app pub date -
Jun 15, 1983
filing date -
Jun 15, 1983
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A data processing system includes an asynchronous parallel multiport volatile main memory system accessible directly by any one of M number of central processing units or by I/O controllers connected in common to any one of N number of system buses. Priority resolver circuits award access to main memory on a predetermined priority basis. Each port includes address, data in, data out, timing and control circuits which operatively couple to the priority resolver circuits. The circuits of each port and the central processing unit or system bus I/O controllers associated therewith operate independently of each other in an asynchronous manner to access and store data and to report errors.
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