Importance

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Abstract

In a DRAM, current surges during sense and restore operations are compensated. Peak current through sense amplifiers is stabilized through initiation of the sense and restore operations during the chip active period and completion of the sense and restore operation during the chip precharge period. The delay between first and second sensing signals is controlled to be longer for those temperature and power supply conditions under which the chip is operating fastest. Correspondingly, the delay between first and second sensing signals is made shorter for those temperature and power supply conditions under which the chip is operating slowest. Overall peak current is limited to that drawn through small transistors used to begin turning on the sense amplifier. The duration of the second sensing signal is responsive to the temperature and power supply variation so it endures for an acceptable period in which to complete the sense and restore function. The second sensing signal timing is not determined by the first sensing signal.

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First Claim