Multistage decoding
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United States of America Patent
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Apr 21, 1987
Issued Date -
N/A
app pub date -
Sep 20, 1984
filing date -
Sep 21, 1983
priority date (Note) -
Expired
status (Latency Note)
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Abstract
An improved row decoding technique for use in a static RAM. Three stages of row decoders are utilized to further decode partially decoded row address signals and combine the decoded signals with a column address signal to enable selected rows of the memory array. To optimize decoding speed, each stage comprises gates which receive only two inputs from the prior stage and the stages are arranged to allow for sharing of signals between adjacent decoders.
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