Random/serial access mode selection circuit for a video memory system
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United States of America Patent
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-
May 5, 1987
Grant Date -
N/A
app pub date -
Dec 30, 1983
filing date -
Dec 30, 1983
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
In a video computer system, an improved memory circuit is provided which is effective for delivering stored data only at appropriate instances, and which is also simpler and more reliable in design. In particular, the system preferably includes a bit-mapped RAM circuit which assumes a serial mode in response to both a row address signal and a suitable data output control signal, and which assumes a parallel or 'random' mode when only the row address is received. Stored data is transferred to a parallel output terminal in the RAM circuit, or to a serial output terminal therein, depending upon the sequence of these signals as well as the column address and read signals, whereby the data output control signal is used for two separate and different purposes within the system.
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