Serially accessed semiconductor memory with tapped shift register
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
May 19, 1987
Grant Date -
N/A
app pub date -
Jan 22, 1985
filing date -
Jan 22, 1985
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A semiconductor memory comprises four arrays (10), (12), (14) and (16) disposed on a single semiconductor chip. Each of the arrays has a serial shift register (86) associated therewith. Data is transferred from the bit lines of the associated array through a transfer gate (90) for storage in the shift register (86). A tap latch (88) is provided on the output of each of the shift bits in the shift register (86) for determining the output therefrom. The tap latch (88) stores a tap decode signal which is decoded from a tap address by the column decoder (30). The column decoder (30) also decodes the column address in the random mode. The tap decode signal selects any of the shift bits in the shift register (86).
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully