Data processing system with a plurality of processors accessing a common bus to interleaved storage
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United States of America Patent
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May 26, 1987
Grant Date -
N/A
app pub date -
Jul 31, 1984
filing date -
Jul 31, 1984
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A plurality of data processor units are connected to a common bus which is connected to first and second interleaved storage units. The system is a synchronous one in which timing means establish a series of information transfer intervals. One or more of the processor units contain apparatus for selectively commencing an address transfer on the bus to one of the storage units during a transfer interval; the storage transaction initiated by the address transfer will require more than the one transfer interval to complete. One or more of the processors have means for monitoring the bus in order to determine whether an address on the bus has been transferred to the first or the second storage unit during a particular transfer interval. The address transfer apparatus further includes apparatus responsive to the monitoring apparatus for selectively transferring the next subsequent address to the other of said storage units to thus achieve alternating interleaving between storage units.
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