Importance

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Abstract

A single chip microcomputer responsive to internal and external instructions in normal and debug modes, respectively, comprises a program counter and first, second, third, and fourth port groups in both of the normal and the debug modes. The first through the fourth port groups are operable in the normal mode to process each internal instruction. Master and slave modes are defined in the debug mode to selectively change operations of the first through the fourth port groups by the use of port controllers to process each external instruction. The master mode is specified by using the first and the second groups as an instruction input port group for each external instruction and as a transfer bus for data related to each external instruction, respectively. In contrast, the third and the fourth port groups are used as an instruction input port group and a transfer bus, respectively. The master and the slave modes are indicated through a single terminal used in the normal mode. The program counter may be left unused in the debug mode. A pair of the microcomputers are connected to each other together with an external device for each external instruction, so as to carry out a debug operation. The debug operation can be voluntarily interrupted and stepwise advanced by the use of a specific instruction representative of jump to present address.

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First Claim