Semiconductor memory having circuit effecting refresh on variable cycles
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United States of America Patent
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Jun 9, 1987
Grant Date -
N/A
app pub date -
Jun 6, 1984
filing date -
Jun 6, 1983
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A semiconductor memory using a dynamic memory device, wherein a battery supplies a power source voltage and a substrate bias voltage when the memory is cut off from an external device, and a refresh control circuit changes in refresh timing of the memory device in accordance with the leakage current of the memory device. The power consumption of the memory can thus be reduced and the data can be kept for an extended period without an external power source.
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