Memory system with operation error detection
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United States of America Patent
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-
Jun 9, 1987
Issued Date -
N/A
app pub date -
Mar 28, 1986
filing date -
Jan 19, 1982
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A memory system for a computer detects data errors, address errors and operation errors to increase the reliability of data stored in the memory system. Address errors are detected by encoding address parity information into the data check field of each memory location. A signal is generated in each memory module indicating the status of operations of that memory module and is transmitted to the processor subsystem of the computer for comparison with a signal indicating the status of operations of the processor subsystem to insure that all memory modules and the memory control in the processor are receiving the same commands.
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